This invention relates to a method for making a capacitor structure for high-density integrated circuits and the structure produced thereby, and more particularly relates to a method for making a Metal Insulator-Metal (MIM) capacitor having a High K (HiK) dielectric constant and the structure produced thereby.
In the semiconductor industry, currently there is a trend towards the use of metal gates for CMOS and HiK dielectric materials in high-density integrated circuit devices. This trend is based on the need to employ metal gates to reduce the problem of high leakage currents that result from device scaling to smaller and smaller dimensions as TOX (Thickness Of silicon Oxide) is reduced as the silicon oxide is thinned down for constant field scaling.
In industry, MIM capacitors are used in integrated circuits, especially those integrated circuits used in Radio frequency (RF) and other high-frequency applications. The requirement for high capacitance density/lower foot print capacitors which are compatible with ever high frequency applications has driven the industry to use HiK dielectric materials for the insulator in the MIM capacitor.
FIGS. 1A-1C are schematic sectional drawings show in three steps in the prior art process of forming a MIM capacitor 10.
FIG. 1A, the basic layers used to form the MIM capacitor 10 are shown on the top of the BEOL structure 12. First a bottom electrode 14 is formed over the BEOL structure 12 followed by formation of a MIM dielectric (MD) layer 16. The MD layer 16 is then covered by a top electrode layer 18 which in turn is covered by an etch stop layer 20. A resist mask 22 is formed over the etch stop layer 20.
FIG. 1B shows the structure 10 of FIG. 1A after the step of etching away those portions of the etch stop layer 20 and the top electrode layer 18 aside from the mask 22 by anisotropic etching down to the MD layer 16. Below the mask 22, the etch stop layer 20 has been shaped into a narrowed etch stop layer 20E and the top electrode layer 18 has been etched to form a top electrode 18E, with both, narrowed etch stop layer 20E and the top electrode layer 18 being aligned with the resist mask 22.
FIG. 1C shows the structure 10 of FIG. 1B after removal of mask 22 followed by etching of a hole extending down through the narrowed etch stop layer 20E to the top surface of the top electrode layer 18 and after etching a pair of holes through the MD layer 16 down to the top surface of the bottom electrode 14. A conductive via 25 has been formed extending down through the narrowed etch stop layer 20E to the top surface of the top electrode 18E. In addition, a dielectric layer 19 has been deposited on the structure 10. Then two conductive vias 27 have been, formed reaching down through the dielectric layer 19 and the MD layer 16 to the top surface of the bottom electrode 14 on either side of the top electrode 18E. The conductive via 25 connects to the top electrode of the BEOL MIM capacitor 10 to wire 26. The conductive vias 27 connect the bottom electrode 14 of the BEOL MIM to wire 28.
Heretofore MIM structures have been integrated into the Back End Of the Line (BEOL) structures of integrated circuit devices. However we have observed that it will eventually be impossible to integrate MIM structures into BEOL structures as the heights of Vias are reduced to smaller and smaller dimensions. Accordingly it is an object of this invention to find an alternative solution which avoids integration of MIM structures into BEOL structures.